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Proceedings Paper

A 2.5 Gb/s CMOS optical transceiver with 10 : 1 serializer using clock generation and delayed data topology
Author(s): Kyung-Min Kim; Hyung-Won Kang; Do-Gyun Kim; Yon-Tae Moon; Young-Wan Choi
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Paper Abstract

We propose the optical transceiver having reference clock generator and CDR with delayed data topology in this paper. The 125MHz reference clock of optical transmitter have been extracted from 10 × 250 Mb/s data arrays. The clock extraction of reference clock generator is achieved by summing the edge information of the each data. Moreover, our optical transmitter includes 2-stacks NMOS serializer scheme rather than 3-stacks conventional scheme to achieve high speed operation. In optical receiver design, we employ a novel CDR with delayed data topology to overcome the problems in conventional CDR such as instability in locking state, nonlinearity output proportional to phase difference, false locking at harmonic frequency. The optical transceiver is designed by using of 0.35μm CMOS technology.

Paper Details

Date Published: 3 March 2006
PDF: 11 pages
Proc. SPIE 6124, Optoelectronic Integrated Circuits VIII, 61241G (3 March 2006); doi: 10.1117/12.645876
Show Author Affiliations
Kyung-Min Kim, Chung-Ang Univ. (South Korea)
Hyung-Won Kang, Chung-Ang Univ. (South Korea)
Do-Gyun Kim, Chung-Ang Univ. (South Korea)
Yon-Tae Moon, Chung-Ang Univ. (South Korea)
Young-Wan Choi, Chung-Ang Univ. (South Korea)


Published in SPIE Proceedings Vol. 6124:
Optoelectronic Integrated Circuits VIII
Louay A. Eldada; El-Hang Lee, Editor(s)

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