Share Email Print

Proceedings Paper

Hybrid integration of a CMOS active quench and reset circuit for a geiger-mode avalanche photodiode
Author(s): Donal Cronin; Alan P. Morrison; Kevin G. McCarthy
Format Member Price Non-Member Price
PDF $17.00 $21.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

An active quench and reset circuit (AQRC) is an essential control circuit for ensuring high-speed photon counting with geiger-mode avalanche photodiodes (GMAPs). Its purpose is to turn off the detector when an avalanche has been detected, register a photon count and then reset the device to its quiescent bias voltage after a preset interval, to enable further avalanche events to be counted. This paper presents an AQRC-IC, developed using Europractice's ASIC Service. The purpose of the design was to develop a high-speed CMOS AQRC for hybrid integration with in-house GMAPs. The designed ASIC, developed using AMS' 3.3 V 0.35 μm CMOS process models, includes a ballast resistor for the external GMAP, a comparator sensing-stage, an active quench and an active reset stage. The hold-off time is determined using external silicon delay lines and an FPGA. The ASIC is implemented on a ceramic DIP as is the GMAP, and the AQRC prototype achieves a saturated count-rate of 5 Mcounts/s, an active quench of 45 ns, an active reset of 30 ns and possible increments of the hold-off time between 50 ns and 500 ns.

Paper Details

Date Published: 3 March 2006
PDF: 10 pages
Proc. SPIE 6124, Optoelectronic Integrated Circuits VIII, 61240R (3 March 2006); doi: 10.1117/12.644108
Show Author Affiliations
Donal Cronin, Univ. College Cork (Ireland)
Alan P. Morrison, Univ. College Cork (Ireland)
Kevin G. McCarthy, Univ. College Cork (Ireland)

Published in SPIE Proceedings Vol. 6124:
Optoelectronic Integrated Circuits VIII
Louay A. Eldada; El-Hang Lee, Editor(s)

© SPIE. Terms of Use
Back to Top