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Proceedings Paper

IIA: a novel method to optimize media instruction set of embedded processor
Author(s): Keming Chen; Guojun Yu; Peng Liu; Qingdong Yao
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Paper Abstract

To accelerate media processing, many media enhancement instructions have been adopted into the instruction set of embedded processors. In this paper, a novel method, called interaction between instructions and algorithms (IIA), is proposed to optimize these media enhancement instructions. Based on the analysis for inherent characteristics of video processing algorithms and processor's architecture, three measures are proposed: three single-cycle instructions for manipulation on bit level are implemented to speed up variable-length decoding; a data path is designed to solve data misalignment in SIMD processing instead of software programs; a memory architecture is proposed to support 128-bit word parallel processing. All these suggestions are used in the optimization of an embedded processor, MediaDSP3200 which fuses RISC architecture and DSP computation capability thoroughly and achieves reduced instruction and 64-bit SIMD instruction set with various addressing mode in a unified RISC pipeline stage architecture. Simulation results show that this optimization method can reduce more than 26.4% of clock cycles for VLD, 47.8% for IDCT and 66.8% for MC in real-time processing.

Paper Details

Date Published: 10 February 2006
PDF: 10 pages
Proc. SPIE 6074, Multimedia on Mobile Devices II, 60740E (10 February 2006); doi: 10.1117/12.643507
Show Author Affiliations
Keming Chen, Zhejiang Univ. (China)
Guojun Yu, Zhejiang Univ. (China)
Peng Liu, Zhejiang Univ. (China)
Qingdong Yao, Zhejiang Univ. (China)


Published in SPIE Proceedings Vol. 6074:
Multimedia on Mobile Devices II
Reiner Creutzburg; Jarmo H. Takala; Chang Wen Chen, Editor(s)

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