Share Email Print
cover

Proceedings Paper

Local-strain effect of the SiN/Si stacking and nano-scale triple gate Si/SiGe MOS transistor
Author(s): C. H. Chang; C. Y. Chou; C. N. Han; C. T. Peng; Kuo-Ning Chiang
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

The tensile strained Si, based on the lattice misfit between Si and SiGe, gives higher speed and higher drive current for the metal oxide silicon field effect transistors. Based on the strained Si technology, a tri-gate CMOS transistor is further applied in the current leakage control and chip performance enhancement. Moreover, the "highly-tensile" silicon nitride capping layer is also applied for the strained Si applications. The stress from the silicon nitride capping layer is uniaxially transferred to the NMOS channel through the source-drain region to create tensile strain in NMOS channel. This paper proposes a finite element method analysis to study the strain distribution of small island size (<200nm) of Si/SiGe strained silicon based tri-gate CMOS transistor and the "highly-tensile" SiNx/Si stacking devices. In the tri-gate CMOS transistor case, the simulation results show that the bending effect from the edge can significantly affect the strain on the surface of the Si channel layer, and a compressive strain or reduced tensile strain occurs at the edge of the Si channel layer. Moreover, the results also indicate that the length of the Si/SiGe channel and the thickness of the Si/SiGe stack layers show significant effects of the strain distribution on the surface of the Si channel layer. In terms of the "highly-tensile" SiNx/Si analysis, the results show that the "highly-tensile" silicon nitride could provide beneficial tensile strain for the channel of the NMOS transistor to enhance the device speed.

Paper Details

Date Published: 5 January 2006
PDF: 7 pages
Proc. SPIE 6035, Microelectronics: Design, Technology, and Packaging II, 60351T (5 January 2006); doi: 10.1117/12.638567
Show Author Affiliations
C. H. Chang, National Tsing Hua Univ. (Taiwan)
C. Y. Chou, National Tsing Hua Univ. (Taiwan)
C. N. Han, National Tsing Hua Univ. (Taiwan)
C. T. Peng, National Tsing Hua Univ. (Taiwan)
Kuo-Ning Chiang, National Tsing Hua Univ. (Taiwan)


Published in SPIE Proceedings Vol. 6035:
Microelectronics: Design, Technology, and Packaging II
Alex J. Hariz, Editor(s)

© SPIE. Terms of Use
Back to Top