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Proceedings Paper

Energy efficient low power shared-memory Fast Fourier Transform (FFT) processor with dynamic voltage scaling
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Paper Abstract

Reduction of power dissipations in CMOS circuits needs to be addressed for portable battery devices. Selection of appropriate transistor library to minimise leakage current, implementation of low power design architectures, power management implementation, and the choice of chip packaging, all have impact on power dissipation and are important considerations in design and implementation of integrated circuits for low power applications. Energy-efficient architecture is highly desirable for battery operated systems, which operates in a wide variation of operating scenarios. Energy-efficient design aims to reconfigure its own architectures to scale down energy consumption depending upon the throughput and quality requirement. An energy efficient system should be able to decide its minimum power requirements by dynamically scaling its own operating frequency, supply voltage or the threshold voltage according to a variety of operating scenarios. The increasing product demand for application specific integrated circuit or processor for independent portable devices has influenced designers to implement dedicated processors with ultra low power requirements. One of these dedicated processors is a Fast Fourier Transform (FFT) processor, which is widely used in signal processing for numerous applications such as, wireless telecommunication and biomedical applications where the demand for extended battery life is extremely high. This paper presents the design and performance analysis of a low power shared memory FFT processor incorporating dynamic voltage scaling. Dynamic voltage scaling enables power supply scaling into various supply voltage levels. The concept behind the proposed solution is that if the speed of the main logic core can be adjusted according to input load or amount of processor's computation "just enough" to meet the requirement. The design was implemented using 0.12 μm ST-Microelectronic 6-metal layer CMOS dual- process technology in Cadence Analogue Environment.

Paper Details

Date Published: 5 January 2006
PDF: 11 pages
Proc. SPIE 6035, Microelectronics: Design, Technology, and Packaging II, 60350A (5 January 2006); doi: 10.1117/12.638354
Show Author Affiliations
D. Fitrio, Victoria Univ. (Australia)
J. Singh, Victoria Univ. (Australia)
A. Stojcevski, Victoria Univ. (Australia)


Published in SPIE Proceedings Vol. 6035:
Microelectronics: Design, Technology, and Packaging II
Alex J. Hariz, Editor(s)

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