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Proceedings Paper

Scaling effects on deep-submicron vertical MOSFETs
Author(s): A. Ahmadi; D. D. Rowlands; K. Alam
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Paper Abstract

Vertical MOSFETs are gaining importance for VLSI circuit integration and for reducing the feature size. They are continuously scaled down in channel length due to the increasing need for higher packing density and higher device speed. Also 3D compaction of circuits is possible using these transistors. In order to achieve as dense and fast as possible circuits several vertical MOSFETs using different technologies have been fabricated. In this paper, 120nm vertical n-channel MOSFET uniformly doped in silicon substrate and channel region is simulated using the ISE_TCAD software, developed by the Integrated Systems Engineering and compared with one of similar fabricated transistors from the literature [4]. The results show more than 92% match between the simulated and the practical devices in terms of terminal characteristics considering the fact that the ideal mobility models as well as the most suitable mesh condition are applied to the simulation flow. Tending to scale down the length of the vertical MOSFETs and observe the short channel effects, transistors with 80nm and 100nm channel length were also simulated. As expected, shrinking the channel length results in increasing the current and decreasing the threshold voltage as part of short channel effects. Other effects such as hot-carrier and substrate current for the three devices were investigated under the certain values of gate and source voltages.

Paper Details

Date Published: 5 January 2006
PDF: 10 pages
Proc. SPIE 6035, Microelectronics: Design, Technology, and Packaging II, 603510 (5 January 2006); doi: 10.1117/12.638298
Show Author Affiliations
A. Ahmadi, Griffith Univ. (Australia)
D. D. Rowlands, Griffith Univ. (Australia)
K. Alam, Griffith Univ. (Australia)


Published in SPIE Proceedings Vol. 6035:
Microelectronics: Design, Technology, and Packaging II
Alex J. Hariz, Editor(s)

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