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Proceedings Paper

ALTA 4700 system mask patterning performance improvements for X-architecture and wafer electrical performance interchangeability with 50kV E-beam
Author(s): Paul C. Allen; Mike Bohan; Eric R. Christenson; H. Dai; M. Duane; H. Christopher Hamaker; Sam C. Howells; Boaz Kenan; Peter Pirogovsky; Malik K. Sadiq; Robin Teitzel; Michael White
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Paper Abstract

The capability and performance of the production-proven DUV ALTA 4300 system has been extended by the development of two new optical subsystems: a 0.9 NA, 42X reduction lens and a high-bandwidth acousto-optic deflector based beam position and intensity correction servo. The PSM overlay performance has been improved by modifications to the software algorithms. The enhanced performance, delivered by these subsystem improvements, has been introduced as a new product-the ALTA 4700. Characterization data show improved resolution performance in line end shortening, through pitch CD bias and feature corner acuity. The AOD subsystem reduces stripe beam placement errors and random and systematic beam intensity errors. This has enabled local CD uniformity to be reduced to 4.3 nm (3σ) and global CD uniformity to be reduced to 6 nm (3σ). Second layer overlay performance is now 20 nm (max error). This paper also demonstrates superior X-Architecture performance delivered by the ALTA 4700. Characterization data show global CD uniformity in 0°, 45°, 90°, and 135° orientations better than 6.5nm (3σ); mean CD control in all 4 orientations less than 3.6nm; and smooth angled lines through a wide range of angles. A split lot wafer evaluation demonstrates the equivalence of wafers produced DUV ALTA system reticles vs. those produced with reticles from a 50kV electron beam system. The evaluation shows the interchangeability of these two systems for 90nm Metal 1 applications-with no changes to the wafer OPC (originally optimized for the 50kV system). Characterization data focus on final wafer electrical performance-the performance characteristic that determines ultimate integrated circuit device yield.

Paper Details

Date Published: 16 June 2005
PDF: 14 pages
Proc. SPIE 5835, 21st European Mask and Lithography Conference, (16 June 2005); doi: 10.1117/12.637280
Show Author Affiliations
Paul C. Allen, Etec Systems, Inc., Applied Materials, Inc. (United States)
Mike Bohan, Etec Systems, Inc., Applied Materials, Inc. (United States)
Eric R. Christenson, Etec Systems, Inc., Applied Materials, Inc. (United States)
H. Dai, Etec Systems, Inc., Applied Materials, Inc. (United States)
M. Duane, Etec Systems, Inc., Applied Materials, Inc. (United States)
H. Christopher Hamaker, Etec Systems, Inc., Applied Materials, Inc. (United States)
Sam C. Howells, Etec Systems, Inc., Applied Materials, Inc. (United States)
Boaz Kenan, Etec Systems, Inc., Applied Materials, Inc. (United States)
Peter Pirogovsky, Etec Systems, Inc., Applied Materials, Inc. (United States)
Malik K. Sadiq, Etec Systems, Inc., Applied Materials, Inc. (United States)
Robin Teitzel, Etec Systems, Inc., Applied Materials, Inc. (United States)
Michael White, Etec Systems, Inc., Applied Materials, Inc. (United States)


Published in SPIE Proceedings Vol. 5835:
21st European Mask and Lithography Conference
Uwe F. W. Behringer, Editor(s)

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