Share Email Print

Proceedings Paper

Back end design and implementation of resilient packet ring ASIC
Author(s): Jishi Li; Fan Zhang; Depeng Jin; Lieguang Zeng
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

Resilient packet ring (RPR) is a good capacity solution to next generation metropolitan area network (MAN). This paper introduces the back end design of RPR application specific integrated circuit (ASIC) designed independently by Department of Electronic Engineering of Tsinghua University. It draws a back end design flow chart and relates about three key techniques: simultaneous switching output (SSO), design for testability (DFT) and static timing analysis (STA). It makes a brief introduction to each technique. It discusses the ways to avoid SSO problems, to calculate scan chains number, to achieve qualified test pattern fault coverage, and to solve STA violations. In the end, it shows design results and layout figure.

Paper Details

Date Published: 5 December 2005
PDF: 8 pages
Proc. SPIE 6022, Network Architectures, Management, and Applications III, 60222G (5 December 2005); doi: 10.1117/12.634027
Show Author Affiliations
Jishi Li, Tsinghua Univ. (China)
Fan Zhang, Tsinghua Univ. (China)
Depeng Jin, Tsinghua Univ. (China)
Lieguang Zeng, Tsinghua Univ. (China)

Published in SPIE Proceedings Vol. 6022:
Network Architectures, Management, and Applications III
Kwok-wai Cheung; Gee-Kung Chang; Guangcheng Li; Ken-Ichi Sato, Editor(s)

© SPIE. Terms of Use
Back to Top