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Proceedings Paper

A video compression platform on a pre-configurable MIMD/SIMD signal processor
Author(s): Gerald Krottendorfer; Rumman Syed
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Paper Abstract

Video decoders have very demanding processing power and data bandwidth requirements, while power dissipation needs to be very low. This paper describes a new video processor platform, which is the first platform in the market capable of even handling high definition multi standard compliant video codec implementations on a fully programmable MIMD/SIMD processor. It can be configured to deliver the exact processing power needs required for a dedicated implementation, saving chip area size and minimizing power dissipation. It is therefore a suitable solution for all kinds of video codec applications, which differ considerably in their processing power needs. Low power design and minimal development and production costs are crucial for this implementation, asking for an optimized architecture, as presented in this paper.

Paper Details

Date Published: 24 June 2005
PDF: 9 pages
Proc. SPIE 5960, Visual Communications and Image Processing 2005, 596047 (24 June 2005); doi: 10.1117/12.633194
Show Author Affiliations
Gerald Krottendorfer, ON DEMAND Microelectronics (Austria)
Rumman Syed, ON DEMAND Microelectronics (Austria)


Published in SPIE Proceedings Vol. 5960:
Visual Communications and Image Processing 2005
Shipeng Li; Fernando Pereira; Heung-Yeung Shum; Andrew G. Tescher, Editor(s)

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