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Proceedings Paper

OPC for edge post structures using chromeless phase shifting mask in 3-D memory
Author(s): Yung-Tin Chen; M.T. Lee
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Paper Abstract

Matrix Semiconductor have successfully implemented chrome-less phase shifting mask to their 0.13μm half pitch, 3D memory circuit process using 0.7NA KrF photolithography. The K1 factor is 0.37. OPC for post structures at the edge of memory array presents a special challenge for 3-D memory circuits. As 3-D memory circuits are stacked vertically, the topography also accumulates to the top of memory layers, thus resulting in reduced process margin due to "peeling off" of edge posts. Ruled based and model based OPC for edge posts are studied in this paper. A simple ruled based OPC is developed to compensate the size difference between the posts at array center and the ones at array edge. A manufacturing oriented OPC strategy is used to gain optimum process windows. The wafer printing results from ruled based OPC are compared to the model prediction from commercial lithography software. Discrepancy between wafer printing results and model prediction using thin film mask approximation is reported. A new model based OPC method for chrome-less PSM in the application to post structures is proposed from this study.

Paper Details

Date Published: 7 November 2005
PDF: 11 pages
Proc. SPIE 5992, 25th Annual BACUS Symposium on Photomask Technology, 599223 (7 November 2005); doi: 10.1117/12.632087
Show Author Affiliations
Yung-Tin Chen, Matrix Semiconductor, Inc. (United States)
M.T. Lee, Taiwan Semiconductor Manufacturing Co. (Taiwan)

Published in SPIE Proceedings Vol. 5992:
25th Annual BACUS Symposium on Photomask Technology
J. Tracy Weed; Patrick M. Martin, Editor(s)

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