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Proceedings Paper

Model-based DRC for design and process integration
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Paper Abstract

Accurately and efficiently verifying the device layout is a crucial step in semiconductor manufacturing. A single missed design violation carries the potential for a disastrous and avoidable yield loss. Typically, design rule checking (DRC) is accomplished by validating drawn layout geometries against pre-determined rules, the specifics of which are derived empirically or from lithographic first principles. These checks are intrinsically rigid, and, taken together, a set of DRC rules only approximate the manufacturable design space in the crudest manner. Process-specific effects are entirely neglected. But for leading-edge technologies, process variations significantly impact the manufacturability of a design, so traditional DRC becomes increasingly difficult to implement, or worse, speciously inaccurate. Fortunately, the rise of Optical Proximity Correction (OPC) has given manufacturers a means to accurately model optical and process effects, and, therefore, an opportunity to introduce this information into the layout validation flow. We demonstrate an enhanced, full-chip DRC technique, which utilizes process models to locate marginal or bad design features and classify them according to severity.

Paper Details

Date Published: 8 November 2005
PDF: 9 pages
Proc. SPIE 5992, 25th Annual BACUS Symposium on Photomask Technology, 59923M (8 November 2005); doi: 10.1117/12.631505
Show Author Affiliations
Chi-Yuan Hung, Semiconductor Manufacturing International Corp. (China)
Andrew M. Jost, Mentor Graphics Corp. (United States)
Qingwei Liu, Semiconductor Manufacturing International Corp. (China)


Published in SPIE Proceedings Vol. 5992:
25th Annual BACUS Symposium on Photomask Technology
J. Tracy Weed; Patrick M. Martin, Editor(s)

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