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Proceedings Paper

Impact of leakage on high performance designs
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Paper Abstract

With aggressive technology scaling there has been a rapid increase in leakage currents in modern CMOS processes. Leakage is mainly composed of sub-threshold and gate leakage. Leakage has been exponentially increasing with the scaling of threshold voltage and gate oxide thickness. This has resulted in power consumption being drastically affected. With the explosive increase in usage of embedded multimedia processors, high performance circuits need to be ultra low power in the standby mode while having a moderate power budget during runtime. One of the most power consuming high performance macros of an embedded processor is the floating point unit. In this paper we look into various macros of a floating point unit designed using a dynamic power optimized logic style called Limited Switch Dynamic Logic and circuit solutions for reducing the impact of leakage on these macros. The results are obtained for CMOS technology nodes of 90nm and 65nm.

Paper Details

Date Published: 16 September 2005
PDF: 10 pages
Proc. SPIE 5910, Advanced Signal Processing Algorithms, Architectures, and Implementations XV, 59100P (16 September 2005); doi: 10.1117/12.617568
Show Author Affiliations
Aniket M. Saha, The Univ. of Texas at Austin (United States)
Earl E. Swartzlander, The Univ. of Texas at Austin (United States)


Published in SPIE Proceedings Vol. 5910:
Advanced Signal Processing Algorithms, Architectures, and Implementations XV
Franklin T. Luk, Editor(s)

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