Share Email Print
cover

Proceedings Paper

Etch modeling in RET synthesis and verification flow
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

The challenges of the 65 nm node and beyond require new formulations of the compact convolution models used in OPC. In addition to simulating more optical and resist effects, these models must accommodate pattern distortions due to etch which can no longer be treated as small perturbations on photo-lithographic effects. (Methods for combining optical and process modules while optimizing the speed/accuracy tradeoff were described in “Advanced Model Formulations for Optical and Process Proximity Correction”, D. Beale et al, SPIE 2004.) In this paper, we evaluate new physics-based etch model formulations that differ from the convolution-based process models used previously. The new models are expressed within the compact modeling framework described by J. Stirniman et al. in SPIE, vol. 3051, p469, 1997, and thus can be used for high-speed process simulation during full-chip OPC.

Paper Details

Date Published: 28 June 2005
PDF: 7 pages
Proc. SPIE 5853, Photomask and Next-Generation Lithography Mask Technology XII, (28 June 2005); doi: 10.1117/12.617143
Show Author Affiliations
Daniel F. Beale, Synopsys Inc. (United States)
James P. Shiely, Synopsys Inc. (United States)


Published in SPIE Proceedings Vol. 5853:
Photomask and Next-Generation Lithography Mask Technology XII
Masanori Komuro, Editor(s)

© SPIE. Terms of Use
Back to Top