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Proceedings Paper

Phase locked-in loop design with pre-specified transient performance
Author(s): Boon Ping Ng; Ying Zhang; Yeng Chai Soh
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Paper Abstract

In this paper, we present a design and a design scheme for the phase locked-in loops satisfying given specifications. The proposed design suggests imposing an additional control signal on the normal input to the variable controlled oscillator (VCO) of the phase locked-in loop (PLL). Based on this design, a scheme of using the second method of Lyapunov is developed to choose the additional control signal and the loop filter parameters of the PLL. The proposed design and design scheme have improved the conventional PLL design results by obtaining a phase locked-in loop with pre-specified performance. The design scheme is based on nonlinear model of the PLL and it is applicable to the design of high order PLLs. Simulations results are reported to demonstrate the effectiveness of the proposed scheme.

Paper Details

Date Published: 15 September 2005
PDF: 8 pages
Proc. SPIE 5907, Photonic Devices and Algorithms for Computing VII, 59070U (15 September 2005); doi: 10.1117/12.616088
Show Author Affiliations
Boon Ping Ng, Singapore Institute of Manufacturing Technology (Singapore)
Nanyang Technological Univ. (Singapore)
Ying Zhang, Singapore Institute of Manufacturing Technology (Singapore)
Yeng Chai Soh, Nanyang Technological Univ. (Singapore)


Published in SPIE Proceedings Vol. 5907:
Photonic Devices and Algorithms for Computing VII
Khan M. Iftekharuddin; Abdul A. S. Awwal, Editor(s)

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