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Proceedings Paper

Divgen: a divider unit generator
Author(s): Romain Michard; Arnaud Tisserand; Nicolas Veyrat-Charvillon
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Paper Abstract

In this work, we present a tool that generates division hardware units. This generator, called divgen, allows a fast and wide space exploration in circuits that involve division operations. The generator produces synthesizable VHDL descriptions of optimized division units for various algorithms and parameters. The results of our generator have been demonstrated on FPGA circuits.

Paper Details

Date Published: 16 September 2005
PDF: 12 pages
Proc. SPIE 5910, Advanced Signal Processing Algorithms, Architectures, and Implementations XV, 59100M (16 September 2005); doi: 10.1117/12.614419
Show Author Affiliations
Romain Michard, CNRS - ENS Lyon - INRIA - UCBL (France)
Arnaud Tisserand, CNRS - ENS Lyon - INRIA - UCBL (France)
Nicolas Veyrat-Charvillon, CNRS - ENS Lyon - INRIA - UCBL (France)


Published in SPIE Proceedings Vol. 5910:
Advanced Signal Processing Algorithms, Architectures, and Implementations XV
Franklin T. Luk, Editor(s)

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