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Proceedings Paper

Impact of overlay metrology on design rule tolerance and shrinkability
Author(s): A. Balasinski; A. J. Walker
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Paper Abstract

Design rule development for next technology generations depends on the progress in the optical and mechanical properties of steppers and photomasks. For two basic types of design rules: those that define minimum critical dimensions (CD, line and space), and those that define overlay/enclosure (OL) between layers, the shrinkpaths with technology nodes are generally unrelated. The min CD rules are dictated by stepper resolution limits and mask minimum features, the overlay rules - by the respective mechanical tolerances of the printing hardware. However, successful shrinks of design databases to the subsequent technology nodes require that all the design rules be scaled, preferably by the same factor. In this work, we first discuss the impact of the different types of rules on the layout architecture. We then show how one derives OL design rules from alignment tolerances. One method is based on the Lynch numbers (LN), corresponding to the misalignment budget ensuring that the OL yield loss is no more than 0.5% per mask level. However, LN’s are not directly measured in the fab. An alternative method is based on the 3s misregistration error. We demonstrate that these two methods show similar results for several types of masks and steppers. Finally, we show how the trend of overlay tolerance (OL) improvement compares with the trend of min feature size (CD) reduction. The data shows an offset between the OL and the CD trends amounting to 14 nm for the 45 nm technology node. This offset, which we call the overlay tolerance gap, means that enclosure rules would, in general, scale at a slower pace compared to the rules dictated by the linear CD shrink. One should note that the OL tolerance is influenced by matching of reticles and steppers and can be improved by the rework of wafers in line. In summary, we discuss theoretical and manufacturing-related aspects of overlay metrology, to advance design rule shrinks aligned with technology roadmap.

Paper Details

Date Published: 10 May 2005
PDF: 8 pages
Proc. SPIE 5752, Metrology, Inspection, and Process Control for Microlithography XIX, (10 May 2005); doi: 10.1117/12.610661
Show Author Affiliations
A. Balasinski, Cypress Semiconductor Corp. (United States)
A. J. Walker, Cypress Semiconductor Corp. (United States)


Published in SPIE Proceedings Vol. 5752:
Metrology, Inspection, and Process Control for Microlithography XIX
Richard M. Silver, Editor(s)

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