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Proceedings Paper

High frequency noise of SOI MOSFETs: performances and limitations (Invited Paper)
Author(s): Francois Danneville; Guillaume Pailloncy; Alexandre Siligaris; Benjamin Iniguez; Gilles Dambrine
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Paper Abstract

In this paper, the performances and limitations related to the high frequency noise properties of SOI MOSFET Technology are investigated. The study is conducted through powerful analytical noise parameters calculation, experimental data, and physical based drift-diffusion noise modeling. In addition to the noise generated by the inner part of the active device, the influence of access resistances, overlap/fringing capacitances, tunneling gate current are discussed qualitatively and quantitatively. The paper ends up with a critical discussion related to the "New Era SOI Technology" to come and its influence on the noise performance.

Paper Details

Date Published: 23 May 2005
PDF: 15 pages
Proc. SPIE 5844, Noise in Devices and Circuits III, (23 May 2005); doi: 10.1117/12.609669
Show Author Affiliations
Francois Danneville, Institut d'Electronique, de Microelectronique et de Nanotechnologie (France)
Guillaume Pailloncy, Institut d'Electronique, de Microelectronique et de Nanotechnologie (France)
Alexandre Siligaris, Institut d'Electronique, de Microelectronique et de Nanotechnologie (France)
Benjamin Iniguez, Univ. Rovira i Virgili (Spain)
Gilles Dambrine, Institut d'Electronique, de Microelectronique et de Nanotechnologie (France)


Published in SPIE Proceedings Vol. 5844:
Noise in Devices and Circuits III
Alexander A. Balandin; Francois Danneville; M. Jamal Deen; Daniel M. Fleetwood, Editor(s)

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