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Proceedings Paper

A combined noise analysis and power supply current based testing of CMOS analog integrated circuits
Author(s): Ashok Srivastava; Vani K. Pulendra; Siva Yellampalli
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Paper Abstract

A technique integrating the noise analysis based testing and the conventional power supply current testing of CMOS analog integrated circuits is presented for bridging type faults due to manufacturing defects. The circuit under test (CUT) is a CMOS amplifier designed for operation at ± 2.5 V and implemented in 1.5 μm CMOS process. The faults simulating possible manufacturing defects have been introduced using the fault injection transistors. The amplifier circuit is analyzed and simulated in SPICE for its performance with and without fault injections. The faults in the CUT are identified by observing the variation in the equivalent noise voltage at the output of CUT. In power supply current testing, the current (IPS) through the power supply voltage, VDD is measured under the application of an AC input stimulus. The effect of parametric variation is taken into consideration by determining the tolerance limit using the Monte-Carlo analysis. The fault is identified if the power supply current, IPS lies outside the deviation given by Monte-Carlo analysis. Simulation results are in close agreement with the corresponding experimental values.

Paper Details

Date Published: 23 May 2005
PDF: 8 pages
Proc. SPIE 5844, Noise in Devices and Circuits III, (23 May 2005); doi: 10.1117/12.609258
Show Author Affiliations
Ashok Srivastava, Louisiana State Univ. (United States)
Vani K. Pulendra, Louisiana State Univ. (United States)
Siva Yellampalli, Louisiana State Univ. (United States)

Published in SPIE Proceedings Vol. 5844:
Noise in Devices and Circuits III
Alexander A. Balandin; Francois Danneville; M. Jamal Deen; Daniel M. Fleetwood, Editor(s)

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