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Proceedings Paper

CHIADO: compilation of high-level computationally intensive algorithms to dynamically reconfigurable computing systems
Author(s): Joao M. P. Cardoso
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Paper Abstract

Reconfigurable computing has already confirmed a significant potential for accelerating certain computing tasks. However, the most successful applications relied on user expertise to design a specific architecture implemented by the hardware structures of the reconfigurable computing device. Hence, one of the most challenging issues is to map, efficiently and automatically, computations (described in software programming languages) to reconfigurable computing devices. This paper presents CHIADO, a research project aiming a compiler framework to map efficiently software programs to reconfigurable computing platforms, especially the ones based on FPGA (Field-Programmable Gate Array) devices. The framework is also intended to support research of new optimization techniques. The project, based on our previous work on compiling Java bytecodes to FPGAs, focuses on high-performance solutions, schemes to estimate the impact of some transformations supported by the compiler (partial/full loop unrolling), and schemes to take advantage of dynamic reconfiguration (e.g., temporal partitioning). This paper gives an overview about the CHIADO project, shows the framework, and enumerates the main project goals.

Paper Details

Date Published: 30 June 2005
PDF: 9 pages
Proc. SPIE 5837, VLSI Circuits and Systems II, (30 June 2005); doi: 10.1117/12.608805
Show Author Affiliations
Joao M. P. Cardoso, Univ. of Algarve (Portugal)
INESC-ID (Portugal)

Published in SPIE Proceedings Vol. 5837:
VLSI Circuits and Systems II
Jose Fco. Lopez; Francisco V. Fernandez; Jose Maria Lopez-Villegas; Jose M. de la Rosa, Editor(s)

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