Share Email Print
cover

Proceedings Paper

A novel low-voltage low-power analogue VLSI implementation of neural networks with on-chip back-propagation learning
Author(s): Manuel Carrasco; Andres Garde; Pilar Murillo; Luis Serrano
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

In this paper a novel design and implementation of a VLSI Analogue Neural Net based on Multi-Layer Perceptron (MLP) with on-chip Back Propagation (BP) learning algorithm suitable for the resolution of classification problems is described. In order to implement a general and programmable analogue architecture, the design has been carried out in a hierarchical way. In this way the net has been divided in synapsis-blocks and neuron-blocks providing an easy method for the analysis. These blocks basically consist on simple cells, which are mainly, the activation functions (NAF), derivatives (DNAF), multipliers and weight update circuits. The analogue design is based on current-mode translinear techniques using MOS transistors working in the weak inversion region in order to reduce both the voltage supply and the power consumption. Moreover, with the purpose of minimizing the noise, offset and distortion of even order, the topologies are fully-differential and balanced. The circuit, named ANNE (Analogue Neural NEt), has been prototyped and characterized as a proof of concept on CMOS AMI-0.5A technology occupying a total area of 2.7mm2. The chip includes two versions of neural nets with on-chip BP learning algorithm, which are respectively a 2-1 and a 2-2-1 implementations. The proposed nets have been experimentally tested using supply voltages from 2.5V to 1.8V, which is suitable for single cell lithium-ion battery supply applications. Experimental results of both implementations included in ANNE exhibit a good performance on solving classification problems. These results have been compared with other proposed Analogue VLSI implementations of Neural Nets published in the literature demonstrating that our proposal is very efficient in terms of occupied area and power consumption.

Paper Details

Date Published: 29 June 2005
PDF: 14 pages
Proc. SPIE 5839, Bioengineered and Bioinspired Systems II, (29 June 2005); doi: 10.1117/12.608794
Show Author Affiliations
Manuel Carrasco, Public Univ. of Navarra (Spain)
Andres Garde, Public Univ. of Navarra (Spain)
Pilar Murillo, Public Univ. of Navarra (Spain)
Luis Serrano, Public Univ. of Navarra (Spain)


Published in SPIE Proceedings Vol. 5839:
Bioengineered and Bioinspired Systems II
Ricardo A. Carmona; Gustavo Linan-Cembrano, Editor(s)

© SPIE. Terms of Use
Back to Top