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Proceedings Paper

A deterministic BIST scheme for test time reduction in VLSI circuits
Author(s): Jose M. Solana
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Paper Abstract

A Built-In Self-Test scheme for VLSI scan-based digital circuits, capable of considerably reducing the number of test cycles, is presented. The core circuit structure consists of a modification of the original scan-based circuit requiring no extra I/O pin. Only a moderate area increment is used to accommodate the extra test circuitry. The structure does not use scan-out, but scan-in exclusively, which implies that the complete circuit responses are observed through the circuit primary-outputs. Based on this structure, a deterministic ROM-based Built-In Self-Test scheme has been developed. In this scheme, the circuit responses are compressed in a Multiple-Input Signature Register. Deterministic test patterns are stored in two ROMs. The first stores the sub-patterns to be serially loaded into the scan chain, while the second stores the sub-patterns to be applied in parallel to the circuit primary inputs. All the control bits for clocks and for selecting the loading of a new sub-pattern into the scan chain are also included in this last ROM. Thus, the clocks and the select-mode input are the only external inputs to the scheme. The comparison of the proposed scheme with a similar one, based on the classical full single-serial scan-path, for a set of benchmark circuits, shows a 19% reduction in ROM-bits, while a reduction of over 45% in the test time is obtained.

Paper Details

Date Published: 30 June 2005
PDF: 12 pages
Proc. SPIE 5837, VLSI Circuits and Systems II, (30 June 2005); doi: 10.1117/12.608657
Show Author Affiliations
Jose M. Solana, Univ. of Cantabria (Spain)

Published in SPIE Proceedings Vol. 5837:
VLSI Circuits and Systems II
Jose Fco. Lopez; Francisco V. Fernandez; Jose Maria Lopez-Villegas; Jose M. de la Rosa, Editor(s)

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