Share Email Print
cover

Proceedings Paper

Search strategy for relevant parasitic elements and reduction of their influence on the operation of SC FIR filters realized in CMOS technology
Author(s): Rafal Dlugosz
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

Parasitic capacities pose a serious problem in switched capacitor finite impulse response (SC FIR) filters realized as VLSI systems in CMOS submicron technologies. The influence of these parasitic elements is especially visible in the stopband of the filter frequency response. To design mixed digital-analog SC FIR filters is a difficult task. Filters of this class have to be designed using full-custom method. SC FIR filters of high orders N are very complex systems with thousands of transistors, capacitors, which, in turn, make the basis for many active elements, switches, delay elements, memories and other circuitry. One of the most important stages during the design process is post-layout HSPICE verification. However, the simulation of separated blocks does not suffice to have enough knowledge of the operation of the whole system. Optimization requires netlist simulations of the entire system, with presence of typically between 5000-30000 of parasitic capacities, where only about hundred of them are critical ones. Analysis which aims at finding these elements, in practice, is not possible because of the complexity of the entire system. The heuristic method of searching for relevant parasitic elements presented in this paper is based on the assumption that all parasitic elements create a set. The main task is to divide this set into subareas. In order to do this particular groups of nets in the layout must be labeled using unique names. Then particular groups of parasitic elements are filtered out from the netlist. Each filtering stage generates two netlists with separate areas of parasitic elements. After the analysis of the simulation results has been done there remains to make the decision concerning subsequent filtering operations. The iteration method is very quick, convenient, efficient and does not require deep knowledge of the simulated system. Many stages of this method can be easy implemented with CAD tools. In realized projects, after no more than 15-60 iterations critical parasitic capacities were found. In realization of the four chips in CMOS 0.8mm and 0.35mm technologies this method issued in very good results-the attenuation in the stopband, which is very important parameter, was improved by about 20-25 dB.

Paper Details

Date Published: 30 June 2005
PDF: 11 pages
Proc. SPIE 5837, VLSI Circuits and Systems II, (30 June 2005); doi: 10.1117/12.608632
Show Author Affiliations
Rafal Dlugosz, Poznan Univ. of Technology (Poland)


Published in SPIE Proceedings Vol. 5837:
VLSI Circuits and Systems II
Jose Fco. Lopez; Francisco V. Fernandez; Jose Maria Lopez-Villegas; Jose M. de la Rosa, Editor(s)

© SPIE. Terms of Use
Back to Top