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Proceedings Paper

SIGEM, low-temperature deposition of poly-SiGe MEMs structures on standard CMOS circuits
Author(s): Juan Ramos-Martos; Joaquin Ceballos-Caceres; Antonio Ragel-Morales; Jose Miguel Mora-Gutierrez; Alberto Arias-Drake; Miguel Angel Lagos-Florido; Jose Maria Munoz-Hinojosa; Anshu Mehta; Agnes Verbist; Bert du Bois; Kersten Kehr; Christina Leinenbach; Steven Van Aerde; Jorg Spengler; Ann Witvrouw
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Paper Abstract

Fabrication of surface-micromachined structures by a post-processing module above standard IC circuits is an efficient way to produce monolithic microsystems, allowing nearly independent optimization of the circuitry and the MEMS process. However, until now the high-temperature steps needed for deposition of poly-Si have limited its application. SiGeM explores the possibilities offered by the low-temperature (450°C) deposition and structuring of poly-SiGe layers, which is compatible with the temperature budget of fully-processed standard IC wafers. In the SiGeM project several low-temperature deposition methods (CVD, PECVD, LPCVD) were developed, and were evaluated with respect to growth rate and material quality. The interconnection technology to the underlying CMOS circuitry was also developed. The capabilities of this new integration technology will be demonstrated in a monolithic high-performance rate-of-turn sensor, currently considered the most demanding MEMs application in terms of material properties of the structural layer (thickness > 10mm, stress gradient < 0.3MPa/mm) and signal processing circuitry (capacitance resolution in the aF range, SNR > 110 dB). System partitioning will combine analog and DSP circuit techniques to maximize resolution and stability. Parasitic electrical coupling within different parts of the system has been analyzed, and countermeasures to reduce it have been incorporated in the design. The feasibility of the approach has already been proved by preliminary characterization of working prototypes containing released microstructures deposited on top of preamplifier circuits built on a 0.35mm, 5-metal, 2-poly, standard CMOS process from Philips Semiconductors. Resonance frequencies are in good agreement with predictions, and quality factors above 8000 have been obtained at pressures of 0.8 mTorr. Measured SNR confirms the capability to achieve a resolution of 0.015°/s over a bandwidth of 50 Hz.

Paper Details

Date Published: 1 July 2005
PDF: 14 pages
Proc. SPIE 5836, Smart Sensors, Actuators, and MEMS II, (1 July 2005); doi: 10.1117/12.608499
Show Author Affiliations
Juan Ramos-Martos, Instituto de Microelectronica de Sevilla (Spain)
Joaquin Ceballos-Caceres, Instituto de Microelectronica de Sevilla (Spain)
Antonio Ragel-Morales, Instituto de Microelectronica de Sevilla (Spain)
Jose Miguel Mora-Gutierrez, Instituto de Microelectronica de Sevilla (Spain)
Alberto Arias-Drake, Instituto de Microelectronica de Sevilla (Spain)
Miguel Angel Lagos-Florido, Instituto de Microelectronica de Sevilla (Spain)
Jose Maria Munoz-Hinojosa, Instituto de Microelectronica de Sevilla (Spain)
Anshu Mehta, Interuniv. MicroElectronics Ctr. (Belgium)
Agnes Verbist, Interuniv. MicroElectronics Ctr. (Belgium)
Bert du Bois, Interuniv. MicroElectronics Ctr. (Belgium)
Kersten Kehr, Robert Bosch GmbH (Germany)
Christina Leinenbach, Robert Bosch GmbH (Germany)
Steven Van Aerde, ASM Belgium (Belgium)
Jorg Spengler, Philips Semiconductors GmbH (Germany)
Ann Witvrouw, Interuniv. MicroElectronics Ctr. (Belgium)

Published in SPIE Proceedings Vol. 5836:
Smart Sensors, Actuators, and MEMS II
Carles Cane; Jung-Chih Chiao; Fernando Vidal Verdu, Editor(s)

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