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Proceedings Paper

Modeling and design of high-order phase locked loops
Author(s): Brian Daniels; Gerard Baldwin; Ronan Farrell
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Paper Abstract

In this paper a new stable high order Digital Phase Lock Loop (DPLL) design technique is proposed. PLLs of order greater than two display better noise bandwidth, Bl, than classical second order PLLs. However these are not unconditionally stable as in the second order case. This technique uses linear theory to design the DPLL. The stability of the DPLL is guaranteed by placing a restriction on the system gain. This stability boundary is found by transforming the system transfer function to the Z-domain and plotting the root locus of the LPLL for values of gain where all the system poles lie inside the unit circle. The minimum value of gain where all the poles lie inside the unit circle forms the stability boundary. It is shown that the stability boundary of the LPLL is comparable to the stability boundary of the DPLL. Finally where the above filter design system produces slow lock, gear shifting of the DPLL components is considered. This allows the DPLL to start off with a wide loop bandwidth and switch to the narrow bandwidth once the system has locked.

Paper Details

Date Published: 30 June 2005
PDF: 10 pages
Proc. SPIE 5837, VLSI Circuits and Systems II, (30 June 2005); doi: 10.1117/12.608485
Show Author Affiliations
Brian Daniels, National Univ. of Ireland Maynooth (Ireland)
Gerard Baldwin, National Univ. of Ireland Maynooth (Ireland)
Ronan Farrell, National Univ. of Ireland Maynooth (Ireland)

Published in SPIE Proceedings Vol. 5837:
VLSI Circuits and Systems II
Jose Fco. Lopez; Francisco V. Fernandez; Jose Maria Lopez-Villegas; Jose M. de la Rosa, Editor(s)

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