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Proceedings Paper

Embedded design-for-testability strategies to test high-resolution SD modulators
Author(s): Sara Escalera; Alvaro Espin; Oscar Guerra; Jose M. de la Rosa; Fernando Medeiro; Belen Perez-Verdu
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Paper Abstract

This paper describes the design-for-testability strategies integrated in a 0.35μm CMOS 17-bit@40-kS/s chopper-stabilized Switched-Capacitor 2-1 cascade ΣΔ modulator for automotive sensor interfaces. After a brief review on the most important effects degrading the circuit performance, a test technique, based on the division of the circuit into several blocks that are tested separately, is presented. Experimental results shows the utility of the implemented test technique to detect errors in the circuit and to characterize the most important blocks with a minimum increase of extra area for the additional test circuitry.

Paper Details

Date Published: 30 June 2005
PDF: 11 pages
Proc. SPIE 5837, VLSI Circuits and Systems II, (30 June 2005); doi: 10.1117/12.608301
Show Author Affiliations
Sara Escalera, Instituto de Microelectronica de Sevilla-CNM-CSIC (Spain)
Alvaro Espin, Instituto de Microelectronica de Sevilla-CNM-CSIC (Spain)
Oscar Guerra, Instituto de Microelectronica de Sevilla-CNM-CSIC (Spain)
Jose M. de la Rosa, Instituto de Microelectronica de Sevilla-CNM-CSIC (Spain)
Fernando Medeiro, Instituto de Microelectronica de Sevilla-CNM-CSIC (Spain)
Belen Perez-Verdu, Instituto de Microelectronica de Sevilla-CNM-CSIC (Spain)


Published in SPIE Proceedings Vol. 5837:
VLSI Circuits and Systems II
Jose Fco. Lopez; Francisco V. Fernandez; Jose Maria Lopez-Villegas; Jose M. de la Rosa, Editor(s)

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