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Proceedings Paper

Application of clock gating techniques at a flip-flop level to switching noise reduction in VLSI circuits
Author(s): Pilar Parra; Javier Castro; Manuel Valencia; Antonio J. Acosta
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Paper Abstract

One of the most important sources of switching noise in large VLSI circuits is the clock-driven circuitry, meaning that memory elements are the main source of noise in digital circuits. This paper faces the application of clock-gating, a well known low-power technique, to the reduction of switching-noise generation. Sources of switching noise in master-slave flip-flops will be analyzed. It will be shown how different solutions for the clock-gated logic show very different results regarding switching-noise generation. Illustrative examples characterized through HSPICE simulations, as well as the application of clock-gating to 16-bit synchronous counter as demonstrator, will provide useful design guidelines for reduction of switching noise generation.

Paper Details

Date Published: 30 June 2005
PDF: 12 pages
Proc. SPIE 5837, VLSI Circuits and Systems II, (30 June 2005); doi: 10.1117/12.608276
Show Author Affiliations
Pilar Parra, Instituto de Microelectronica de Sevilla-CNM-CSIC (Spain)
Univ. de Sevilla (Spain)
Javier Castro, Instituto de Microelectronica de Sevilla-CNM-CSIC (Spain)
Manuel Valencia, Instituto de Microelectronica de Sevilla-CNM-CSIC (Spain)
Univ. de Sevilla (Spain)
Antonio J. Acosta, Instituto de Microelectronica de Sevilla-CNM-CSIC (Spain)
Univ. de Sevilla (Spain)


Published in SPIE Proceedings Vol. 5837:
VLSI Circuits and Systems II
Jose Fco. Lopez; Francisco V. Fernandez; Jose Maria Lopez-Villegas; Jose M. de la Rosa, Editor(s)

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