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Proceedings Paper

Performance analysis of full adders in CMOS technologies
Author(s): Javier Castro; Pilar Parra; Antonio J. Acosta
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Paper Abstract

Full adders are one of the most important building blocks in VLSI digital arithmetic. The area, electrical, timing, power consumed and noise generated characteristics of this cell are strongly dependent on the design technique. An exhaustive work taking into account the above parameters is done, and that complete analysis will be of utility for the community of digital designers. Emphasis will be done in power/noise figures, of most important concern in current CMOS mixed-signal design. The full adders considered are those using complementary CMOS, pass-transistor logic, double pass-transistor logic, and two versions based on CMOS transmission gate. Main parameters as area, delay, power consumption and noise generation have been measured by electrical simulation in a 0.35 μm CMOS technology. The main results obtained are, on one hand, the selection of a logic family for a specific application and, on the other hand, the selection of a specific full adder structure for an optimized parameter option -power, noise or speed.

Paper Details

Date Published: 30 June 2005
PDF: 10 pages
Proc. SPIE 5837, VLSI Circuits and Systems II, (30 June 2005); doi: 10.1117/12.608269
Show Author Affiliations
Javier Castro, Instituto de Microelectronica de Sevilla-CNM-CSIC (Spain)
Pilar Parra, Instituto de Microelectronica de Sevilla-CNM-CSIC (Spain)
Univ. de Sevilla (Spain)
Antonio J. Acosta, Instituto de Microelectronica de Sevilla-CNM-CSIC (Spain)
Univ. de Sevilla (Spain)


Published in SPIE Proceedings Vol. 5837:
VLSI Circuits and Systems II
Jose Fco. Lopez; Francisco V. Fernandez; Jose Maria Lopez-Villegas; Jose M. de la Rosa, Editor(s)

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