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Proceedings Paper

Design of a 12-bit 80MS/s pipeline analog-to-digital converter for PLC-VDSL applications
Author(s): Jesus Ruiz-Amaya; Manuel Delgado-Restituto; Juan F. Fernandez-Bootello; Jose M. de la Rosa
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Paper Abstract

This paper describes the design of a 12-bit 80MS/s pipeline Analog-to-Digital converter implemented in 0.13mm CMOS logic technology. The design has been computer-aided by a developed toolbox for the simulation, synthesis and verification of Nyquist-Rate Analog-to-Digital and Digital-to-Analog Converters in MATLAB. The embedded simulator uses SIMULINK C-coded S-functions to model all required subcircuits including their main error mechanisms. This approach allows to drastically speed up the simulation CPU-time and makes the proposed tool an advantageous alternative for fast exploration of requirements and as a design validation tool. The converter is based on a 10-stage pipeline preceded by a sample/hold with bootstrapping technique. Each stage gives 1.5 effective bits, except for the first one which provides 2.5 effective bits to improve linearity. The Analog-to-Digital architecture uses redundant bits for digital correction, it is planned to be implemented without using calibration and employs a subranging pipeline look-ahead technique to increase speed. Substrate biased MOSFETs in the depletion region are used as capacitors, linearized by a series compensation. Simulation results show that the Multi-Tone Power Ratio is higher than 56dB for several DMT test signals and the estimated Signal-to-Noise Ratio yield is supposed to be better than 62 dB from DC to Nyquist frequency. The converter dissipates less than 150mW from a 3.3V supply and occupies less than 4 mm2 die area. The results have been checked with all process corners from -40° to 85° and power supply from 3V to 3.6V.

Paper Details

Date Published: 30 June 2005
PDF: 8 pages
Proc. SPIE 5837, VLSI Circuits and Systems II, (30 June 2005); doi: 10.1117/12.608268
Show Author Affiliations
Jesus Ruiz-Amaya, Instituto de Microelectronica de Sevilla, Ctr. Nacional de Microelectronica (Spain)
Manuel Delgado-Restituto, Instituto de Microelectronica de Sevilla, Ctr. Nacional de Microelectronica (Spain)
Juan F. Fernandez-Bootello, Instituto de Microelectronica de Sevilla, Ctr. Nacional de Microelectronica (Spain)
Jose M. de la Rosa, Instituto de Microelectronica de Sevilla, Ctr. Nacional de Microelectronica (Spain)


Published in SPIE Proceedings Vol. 5837:
VLSI Circuits and Systems II
Jose Fco. Lopez; Francisco V. Fernandez; Jose Maria Lopez-Villegas; Jose M. de la Rosa, Editor(s)

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