Share Email Print
cover

Proceedings Paper

A low-cost bidimensional smart pixel network for video coding operations
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

Optimum visual and hearing qualities at high compression ratios as well as reduced area/power dissipation are key factors for actual and future commercial mobile multimedia devices. In this sense, a real time Smart Pixels Array designed to perform efficiently key video coding operations is presented in this paper. In particular, the array introduced is capable to perform the Discrete Wavelet Transform (DWT), Zerotree Entropy (ZTE) Coding and Frame Differencing (FD) over SQCIF images (128×96 pixels) by dividing them into wavelet blocks (8×8 pixels). In order to perform these tasks, the array has been designed as a bidimensional network of interconnected smart pixel processors working in a massively parallel fashion, allowing the operation at very low clock frequencies and hence, low power dissipation. Each of these smart pixels is composed by a photodetector, an analog-digital converter in order to obtain a digital representation of the light intensity received by the photodetector and a Ferroelectric Liquid Crystal placed over the whole surface of the pixel to display the image. Additionally, each pixel has a dedicated circuitry associated which performs all the specific computations related with the three video coding operations previously mentioned, exhibiting a power dissipation of 4.15 μW@128 kHz and a square area of 110x110 μm2 using a 0.25 μm CMOS technology. The array has been integrated into a mobile multimedia device prototype, fully designed at our research centre, capable to send and receive compressed audio and video information with a total power consumption of 1.36 W in an area of 351.5 mm2.

Paper Details

Date Published: 30 June 2005
PDF: 12 pages
Proc. SPIE 5837, VLSI Circuits and Systems II, (30 June 2005); doi: 10.1117/12.608263
Show Author Affiliations
S. Lopez, Univ. of Las Palmas de Gran Canaria (Spain)
G. M. Callico, Univ. of Las Palmas de Gran Canaria (Spain)
J. F. Lopez, Univ. of Las Palmas de Gran Canaria (Spain)
R. Sarmiento, Univ. of Las Palmas de Gran Canaria (Spain)


Published in SPIE Proceedings Vol. 5837:
VLSI Circuits and Systems II
Jose Fco. Lopez; Francisco V. Fernandez; Jose Maria Lopez-Villegas; Jose M. de la Rosa, Editor(s)

© SPIE. Terms of Use
Back to Top