Share Email Print

Proceedings Paper

Voltage-buffer-based low-power area-efficient SC FIR filter for wireless communication
Author(s): Rafal Dlugosz; Ryszard Wojtyna
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

In this paper, a new idea of finite impulse response (FIR) switched capacitor (SC) filter realization suitable for a wireless communication is proposed. A design on the circuit level for a CMOS 0.35 μm process is presented. Main advantages of the proposed filter are low power consumption and small chip area occupation. In classic approaches to SC FIR filter realizations, such parameters like chip area, power consumption and signal quality are conflicting ones. There are various SC FIR architectures. Some are power economic, but need very complicated circuitry. Others have simple structures, but use a big number of high power active elements like operational amplifiers. We propose an approach, which is a compromise solution. Instead of using high power op amps, specialized low-power simple voltage followers have been introduced to reduce the chip area occupation and simultaneously not enlarge the power consumption. The proposed idea is to decrease the number of large capacitors by providing to some big capacitors a voltage from several small capacitors by means of the specialized voltage followers. Apart from power-economic operation, our followers are simple, including 8 transistors, and operate with high precision (of order 10-3). The resulting SC FIR filters dissipate relatively low power. Wireless channel filters based on SC FIR techniques are typically of the order 30 to 35. The proposed filter is designed just for such an order, and will dissipate less than 6 mW, being supplied by 3V, and occupies a chip area less than 1.5 mm2. The maximum signal frequency is close to 1.25 MHz. For a proper operation, the circuit needs only a 2.5 MHz clock generator, which is a low value. The clock generator is realized as an internal block, similarly as in our previous chips implemented in CMOS 0.8 μm and 0.35 μm processes.

Paper Details

Date Published: 30 June 2005
PDF: 12 pages
Proc. SPIE 5837, VLSI Circuits and Systems II, (30 June 2005); doi: 10.1117/12.608241
Show Author Affiliations
Rafal Dlugosz, Poznan Univ. of Technology (Poland)
Ryszard Wojtyna, Univ. of Technology and Agriculture (Poland)

Published in SPIE Proceedings Vol. 5837:
VLSI Circuits and Systems II
Jose Fco. Lopez; Francisco V. Fernandez; Jose Maria Lopez-Villegas; Jose M. de la Rosa, Editor(s)

© SPIE. Terms of Use
Back to Top