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Proceedings Paper

AER synthetic generation in hardware for bio-inspired spiking systems
Author(s): Alejandro Linares-Barranco; Bernabe Linares-Barranco; Gabriel Jimenez-Moreno; Anton Civit-Balcells
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Paper Abstract

Address Event Representation (AER) is an emergent neuromorphic interchip communication protocol that allows for real-time virtual massive connectivity between huge number neurons located on different chips. By exploiting high speed digital communication circuits (with nano-seconds timings), synaptic neural connections can be time multiplexed, while neural activity signals (with mili-seconds timings) are sampled at low frequencies. Also, neurons generate 'events' according to their activity levels. More active neurons generate more events per unit time, and access the interchip communication channel more frequently, while neurons with low activity consume less communication bandwidth. When building multi-chip muti-layered AER systems it is absolutely necessary to have a computer interface that allows (a) to read AER interchip traffic into the computer and visualize it on screen, and (b) convert conventional frame-based video stream in the computer into AER and inject it at some point of the AER structure. This is necessary for test and debugging of complex AER systems. This paper addresses the problem of converting, in a computer, a conventional frame-based video stream into the spike event based representation AER. There exist several proposed software methods for synthetic generation of AER for bio-inspired systems. This paper presents a hardware implementation for one method, which is based on Linear-Feedback-Shift-Register (LFSR) pseudo-random number generation. The sequence of events generated by this hardware, which follows a Poisson distribution like a biological neuron, has been reconstructed using two AER integrator cells. The error of reconstruction for a set of images that produces different traffic loads of event in the AER bus is used as evaluation criteria. A VHDL description of the method, that includes the Xilinx PCI Core, has been implemented and tested using a general purpose PCI-AER board. This PCI-AER board has been developed by authors, and uses a Spartan II 200 FPGA. This system for AER Synthetic Generation is capable of transforming frames of 64x64 pixels, received through a standard computer PCI bus, at a frame rate of 25 frames per second, producing spike events at a peak rate of 107 events per second.

Paper Details

Date Published: 29 June 2005
PDF: 8 pages
Proc. SPIE 5839, Bioengineered and Bioinspired Systems II, (29 June 2005); doi: 10.1117/12.608192
Show Author Affiliations
Alejandro Linares-Barranco, Univ. de Sevilla (Spain)
Bernabe Linares-Barranco, Instituto de Microelectronica de Sevilla (Spain)
Gabriel Jimenez-Moreno, Univ. de Sevilla (Spain)
Anton Civit-Balcells, Univ. de Sevilla (Spain)

Published in SPIE Proceedings Vol. 5839:
Bioengineered and Bioinspired Systems II
Ricardo A. Carmona; Gustavo Linan-Cembrano, Editor(s)

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