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Proceedings Paper

Technology mapping in library-free logic synthesis
Author(s): Jingyue Xue; Dhamin Al-Khalili; Come N. Rozon
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Paper Abstract

Library-free logic synthesis is an innovative approach that provides a fully customized design performance while avoiding the huge cost of developing and maintaining the extensive cell libraries. Its strength is coming from the use of a virtual library based on on-the-fly cell generation. However, the flexibility of the virtual library makes it impossible to exploit the existing methodologies that are based on the pre-characterized standard cell libraries. The authors developed a creative approach to map the design into customized CMOS complex gates using virtual library technique. This is a timing-driven process, which consists of four phases: logic transformation, logic partitioning, gate mapping and transistor re-ordering. The performance of CMOS complex gates and the logic path derived from the extracted transistor topology are used in guiding the synthesis process. The proposed mapping algorithm was used in combination with our topology-based performance estimation model to synthesize some of the MCNC91 benchmarks. The results show that our algorithm can achieve 42% improvement in area and 43% improvement in power compared to that same designs synthesized by Synposys' Design Analyzer.

Paper Details

Date Published: 30 June 2005
PDF: 10 pages
Proc. SPIE 5837, VLSI Circuits and Systems II, (30 June 2005); doi: 10.1117/12.608154
Show Author Affiliations
Jingyue Xue, Royal Military College of Canada (Canada)
Dhamin Al-Khalili, Royal Military College of Canada (Canada)
Come N. Rozon, Royal Military College of Canada (Canada)

Published in SPIE Proceedings Vol. 5837:
VLSI Circuits and Systems II
Jose Fco. Lopez; Francisco V. Fernandez; Jose Maria Lopez-Villegas; Jose M. de la Rosa, Editor(s)

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