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Proceedings Paper

Algorithms to get the maximum operation frequency for skew-tolerant clocking schemes
Author(s): D. Guerrero; M. Bellido; J. Juan; A. Millan; P. Ruiz; E. Ostua; J. Viejo
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Paper Abstract

Nowadays it is not possible to neglect the delay of interconnection lines. The die size is rising very fast, and the delay of the interconnection lines grows quadrically with it. Also, the fact that the gate delay keeps getting smaller increases the importance of the delay of the interconnection lines. The delay of the clock lines is specially important: If the clock skew is underestimated and the clocking scheme is not properly designed, then the system may not work under any clock frequency. In this paper we evaluate the timing performance of three skew-tolerant clocking schemes. These schemes are the well known Master-Slave clocking scheme (MS) and two schemes developed by the authors: Parallel Alternating Latches Clocking Scheme (PALACS) and four-phase Parallel Alternating Latches Clocking Scheme (four-phase PALACS). To carry out these analysis, the authors introduce new algorithms to obtain the clock waveforms required by a synchronous sequential circuit. Separated algorithms were developed for every clocking scheme. The algorithms take a set of timing parameters as input and generate a chronogram of the circuit trying to minimise the clock period but ensuring the timing restrictions of the circuit are met for a given clock skew. Using these algorithms is it possible to draw a representation of the computation frequency as a function of the clock skew for every clock scheme. Once we have estimated the timing parameters and the skew, these representations can help us to choose the best clocking scheme for our design.

Paper Details

Date Published: 30 June 2005
PDF: 12 pages
Proc. SPIE 5837, VLSI Circuits and Systems II, (30 June 2005); doi: 10.1117/12.608064
Show Author Affiliations
D. Guerrero, Microelectronic Institute of Seville-CNM (Spain)
Univ. of Seville (Spain)
M. Bellido, Microelectronic Institute of Seville-CNM (Spain)
Univ. of Seville (Spain)
J. Juan, Microelectronic Institute of Seville-CNM (Spain)
Univ. of Seville (Spain)
A. Millan, Microelectronic Institute of Seville-CNM (Spain)
Univ. of Seville (Spain)
P. Ruiz, Microelectronic Institute of Seville-CNM (Spain)
Univ. of Seville (Spain)
E. Ostua, Microelectronic Institute of Seville-CNM (Spain)
Univ. of Seville (Spain)
J. Viejo, Microelectronic Institute of Seville-CNM (Spain)
Univ. of Seville (Spain)


Published in SPIE Proceedings Vol. 5837:
VLSI Circuits and Systems II
Jose Fco. Lopez; Francisco V. Fernandez; Jose Maria Lopez-Villegas; Jose M. de la Rosa, Editor(s)

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