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Proceedings Paper

Continuous-time cascaded ΣΔ modulators for VDSL: a comparative study
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Paper Abstract

This paper describes new cascaded continuous-time ΣΔ modulators intended to cope with very high-rate digital subscriber line specifications, i.e. 12-bit resolution within a 20-MHz signal bandwidth. These modulators have been synthesized using a new methodology that is based on the direct synthesis of the whole cascaded architecture in the continuous-time domain instead of using a discrete-to-continuous time transformation as has been done in previous approaches. This method allows to place the zeroes/poles of the loop-filter transfer function in an optimal way and to reduce the number of analog components, namely: transconductors and/or amplifiers, resistors, capacitors and digital-to-analog converters. This leads to more efficient topologies in terms of circuitry complexity, power consumption and robustness with respect to circuit non-idealities. A comparison study of the synthesized architectures is done considering their sensitivity to most critical circuit error mechanisms. Time-domain behavioral simulations are shown to validate the presented approach.

Paper Details

Date Published: 30 June 2005
PDF: 12 pages
Proc. SPIE 5837, VLSI Circuits and Systems II, (30 June 2005); doi: 10.1117/12.607923
Show Author Affiliations
Ramon Tortosa, Instituto de Microelectronica de Sevilla-CNM-CSIC (Spain)
Jose M. de la Rosa, Instituto de Microelectronica de Sevilla-CNM-CSIC (Spain)
Angel Rodriguez-Vazquez, Instituto de Microelectronica de Sevilla-CNM-CSIC (Spain)
Francisco V. Fernandez, Instituto de Microelectronica de Sevilla-CNM-CSIC (Spain)

Published in SPIE Proceedings Vol. 5837:
VLSI Circuits and Systems II
Jose Fco. Lopez; Francisco V. Fernandez; Jose Maria Lopez-Villegas; Jose M. de la Rosa, Editor(s)

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