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Proceedings Paper

A digital pixel cell for address event representation image convolution processing
Author(s): Luis Camunas-Mesa; Antonio Acosta-Jimenez; Teresa Serrano-Gotarredona; Bernabe Linares-Barranco
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Paper Abstract

Address Event Representation (AER) is an emergent neuromorphic interchip communication protocol that allows for real-time virtual massive connectivity between huge number of neurons located on different chips. By exploiting high speed digital communication circuits (with nano-seconds timings), synaptic neural connections can be time multiplexed, while neural activity signals (with mili-seconds timings) are sampled at low frequencies. Also, neurons generate events according to their information levels. Neurons with more information (activity, derivative of activities, contrast, motion, edges,...) generate more events per unit time, and access the interchip communication channel more frequently, while neurons with low activity consume less communication bandwidth. AER technology has been used and reported for the implementation of various type of image sensors or retinae: luminance with local agc, contrast retinae, motion retinae,... Also, there has been a proposal for realizing programmable kernel image convolution chips. Such convolution chips would contain an array of pixels that perform weighted addition of events. Once a pixel has added sufficient event contributions to reach a fixed threshold, the pixel fires an event, which is then routed out of the chip for further processing. Such convolution chips have been proposed to be implemented using pulsed current mode mixed analog and digital circuit techniques. In this paper we present a fully digital pixel implementation to perform the weighted additions and fire the events. This way, for a given technology, there is a fully digital implementation reference against which compare the mixed signal implementations. We have designed, implemented and tested a fully digital AER convolution pixel. This pixel will be used to implement a full AER convolution chip for programmable kernel image convolution processing.

Paper Details

Date Published: 29 June 2005
PDF: 12 pages
Proc. SPIE 5839, Bioengineered and Bioinspired Systems II, (29 June 2005); doi: 10.1117/12.607709
Show Author Affiliations
Luis Camunas-Mesa, Instituto de Microelectronica de Sevilla, National Microelectronics Ctr., Spanish Research Council (Spain)
Antonio Acosta-Jimenez, Instituto de Microelectronica de Sevilla, National Microelectronics Ctr., Spanish Research Council (Spain)
Teresa Serrano-Gotarredona, Instituto de Microelectronica de Sevilla, National Microelectronics Ctr., Spanish Research Council (Spain)
Bernabe Linares-Barranco, Instituto de Microelectronica de Sevilla, National Microelectronics Ctr., Spanish Research Council (Spain)


Published in SPIE Proceedings Vol. 5839:
Bioengineered and Bioinspired Systems II
Ricardo A. Carmona; Gustavo Linan-Cembrano, Editor(s)

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