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Proceedings Paper

Efficient N X N Bit Parallel Architecture Based On Ancient Indian Vedic Mathematics
Author(s): Himanshu Thapliyal
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Date Published:
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Proc. SPIE 5837, VLSI Circuits and Systems II, ; doi: 10.1117/12.607695
Show Author Affiliations
Himanshu Thapliyal, International Institute of Information Technology (India)


Published in SPIE Proceedings Vol. 5837:
VLSI Circuits and Systems II
Jose Fco. Lopez; Francisco V. Fernandez; Jose Maria Lopez-Villegas; Jose M. de la Rosa, Editor(s)

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