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Proceedings Paper

A continuous time low-pass sigma delta modulator implemented with transmission lines
Author(s): L. Hernandez; P. Rombouts; E. Prefasi; S. Paton; M. Garcia; C. Lopez
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Paper Abstract

This work presents a prototype low pass continuous time sigma delta modulator which uses transmission lines in its loop filter rather than capacitive integrators. As has been shown in prior theoretical work, such a structure allows to desensitize the modulator against clock jitter and excess loop delay. The parameters of the analog components of this design are independent of the sampling clock, as long as the clock frequency has to fit only with the length of the external transmission lines. The prototype single-bit modulator was designed for an oversampling ratio of 128. When the modulator is clocked at 53.7MHz achieves a peak SNR of 67 dB. In an experiment with an excessive clock jitter of 1% of the clock period and a test tone of -10dBfs is applied, the SNDR is degraded by only 5dB compared to the case without jitter.

Paper Details

Date Published: 30 June 2005
PDF: 7 pages
Proc. SPIE 5837, VLSI Circuits and Systems II, (30 June 2005); doi: 10.1117/12.607359
Show Author Affiliations
L. Hernandez, Univ. Carlos III de Madrid (Spain)
P. Rombouts, ELIS Ghent Univ. (Belgium)
E. Prefasi, Univ. Carlos III de Madrid (Spain)
S. Paton, Univ. Carlos III de Madrid (Spain)
M. Garcia, Univ. Carlos III de Madrid (Spain)
C. Lopez, Univ. Carlos III de Madrid (Spain)


Published in SPIE Proceedings Vol. 5837:
VLSI Circuits and Systems II
Jose Fco. Lopez; Francisco V. Fernandez; Jose Maria Lopez-Villegas; Jose M. de la Rosa, Editor(s)

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