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Proceedings Paper

Inter-layer vias and TESH interconnection network for a 3-D heterogeneous sensor system on a chip
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Paper Abstract

In a previous paper we had described a novel concept on ultra-small, ultra-compact, unattended multi-phenomenological sensor systems for rapid deployment, with integrated classification-and-decision-information extraction capability from the sensed environment. Specifically, we had proposed placing such integrated capability on a 3-D Heterogeneous System on a Chip (HSoC). This paper amplifies two key aspects of that future sensor technology. These are the creation of inter-layer vias by high aspect ratio MPS (Macro Porous Silicon) process, and the adaptation of the TESH (Tori connected mESHes) network to bind the diverse leaf nodes on multiple layers of the 3-D structure. Interesting also is the inter-relationship between these two aspects. In particular, the issue of overcoming via failures, catastrophic as well as high-resistance failures, through the existence of alternative paths in the TESH network and corresponding routing strategies is discussed. A probabilistic model for via failures is proposed and the testing of the vias between the sensor layer and the adjacent processing layer is discussed.

Paper Details

Date Published: 27 May 2005
PDF: 12 pages
Proc. SPIE 5796, Unattended Ground Sensor Technologies and Applications VII, (27 May 2005); doi: 10.1117/12.606938
Show Author Affiliations
Shekhar Bhansali, Univ. of South Florida (United States)
Glenn Chapman, Simon Fraser Univ. (Canada)
Vijay Jain, Univ. of South Florida (United States)


Published in SPIE Proceedings Vol. 5796:
Unattended Ground Sensor Technologies and Applications VII
Edward M. Carapezza, Editor(s)

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