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Proceedings Paper

MAID: manufacturing aware IC design
Author(s): Louis K. Scheffer
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Paper Abstract

Design tools should take manufacturing foibles into account, on this everyone agrees. But specifically, which DFM issues should IC design software take into account, and how should they be conveyed from the fab to the design tools? Here we examine an approach that expresses four of the most pressing DFM concerns - point defect densities, via yield, lithographic process windows, and cell yield - in a way design tools can easily understand. We show these data types can be combined, they can be read quickly, and that they allow designs to be analyzed (and potentially optimized) with speeds commensurate with other existing algorithms that run on large designs. The major concern that remains is getting useful DFM data from the manufacturing firms. Without this, for example, IC design tools cannot trade off one effect against another.

Paper Details

Date Published: 5 May 2005
PDF: 12 pages
Proc. SPIE 5756, Design and Process Integration for Microelectronic Manufacturing III, (5 May 2005); doi: 10.1117/12.605371
Show Author Affiliations
Louis K. Scheffer, Cadence Design Systems, Inc. (United States)


Published in SPIE Proceedings Vol. 5756:
Design and Process Integration for Microelectronic Manufacturing III
Lars W. Liebmann, Editor(s)

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