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Proceedings Paper

Real-time processor for staring receivers
Author(s): Brian R. Hanzal; Andrzej Peczalski; James C. Schwanebeck; Richard B. Sanderson; Eric R. Fossum
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Paper Abstract

The design, fabrication, and testing of a state-of-the-art, high-throughput on-focal plane IR-image signal processor is described. The processing functions performed are frame differencing and thresholding. The final focal plane array will consist of a 128 x 128-pixel platinum-silicide detector bump-mounted to an on-chip CCD multiplexer. The processor is in a 128-channel parallel-pipeline format. Each channel consists of a pixel regenerator (charge differencer), 128-pixel frame store CCD memory, pixel differencer, second pixel regenerator, thresholder (analog comparator), and digital latch. Four parallel analog outputs and four parallel digital outputs are included. The digital outputs provide a bit map of the image. All analog clock signals (128 KHz, 256 KHz, and 5 MHz) are generated by on-chip TTL-input clock drivers. TTL clock driver inputs are generated off-chip. The technology is low-temperature surface and buried channel CCD/CMOS/indium bump. The design goal was 8-bit resolution at 77 K and 1000 frames/s. Applications include point- or extended-target motion detection with thresholding. Design trade-offs and enhancements (such as on-chip detector gain compensation and a simple window processor) are discussed.

Paper Details

Date Published: 1 July 1992
PDF: 10 pages
Proc. SPIE 1684, Infrared Readout Electronics, (1 July 1992); doi: 10.1117/12.60515
Show Author Affiliations
Brian R. Hanzal, Honeywell Systems and Research Ctr. (United States)
Andrzej Peczalski, Honeywell Systems and Research Ctr. (United States)
James C. Schwanebeck, Honeywell Systems and Research Ctr. (United States)
Richard B. Sanderson, Air Force Wright Lab. (United States)
Eric R. Fossum, Jet Propulsion Lab. (United States)


Published in SPIE Proceedings Vol. 1684:
Infrared Readout Electronics
Eric R. Fossum, Editor(s)

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