Share Email Print

Proceedings Paper

Optimization of cryogenic CMOS processes for sub-10°K applications
Author(s): Robert M. Glidden; Steven C. Lizotte; James S. Cable; Larry W. Mason; Chipaul Cao
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

Below approximately 40°K, conventional CMOS technologies show radical departures from room temperature behavior and classical theory, confounding attempts to design readout circuits that have desirable and predictable behavior. Though the effects often seem difficult to explain, they are in all cases due to the effects of carrier freezeout. We have extensively investigated the device properties of CMOS PETs at temperatures very close to absolute zero and conducted a series of process optimizations designed to overcome anomalies that dominate the device behavior. The resulting technology has been used to build readouts for very long wavelength extrinsic silicon detectors, including staring arrays of significant complexity (256x256 pixels). Large die sizes (450 mils) have been produced with high yields (in excess of 50 percent) using this process.

Paper Details

Date Published: 1 July 1992
PDF: 38 pages
Proc. SPIE 1684, Infrared Readout Electronics, (1 July 1992); doi: 10.1117/12.60492
Show Author Affiliations
Robert M. Glidden, TRW Electronic Systems Group (United States)
Steven C. Lizotte, TRW Electronic Systems Group (United States)
James S. Cable, TRW Electronic Systems Group (United States)
Larry W. Mason, TRW Electronic Systems Group (United States)
Chipaul Cao, TRW Electronic Systems Group (United States)

Published in SPIE Proceedings Vol. 1684:
Infrared Readout Electronics
Eric R. Fossum, Editor(s)

© SPIE. Terms of Use
Back to Top