Share Email Print
cover

Proceedings Paper

A high data rate universal lattice decoder on FPGA
Author(s): Jing Ma; Xinming Huang; Swapna Kura
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

This paper presents the architecture design of a high data rate universal lattice decoder for MIMO channels on FPGA platform. A phost strategy based lattice decoding algorithm is modified in this paper to reduce the complexity of the closest lattice point search. The data dependency of the improved algorithm is examined and a parallel and pipeline architecture is developed with the iterative decoding function on FPGA and the division intensive channel matrix preprocessing on DSP. Simulation results demonstrate that the improved lattice decoding algorithm provides better bit error rate and less iteration number compared with the original algorithm. The system prototype of the decoder shows that it supports data rate up to 7Mbit/s on a Virtex2-1000 FPGA, which is about 8 times faster than the original algorithm on FPGA platform and two-orders of magnitude better than its implementation on a DSP platform.

Paper Details

Date Published: 2 June 2005
PDF: 11 pages
Proc. SPIE 5819, Digital Wireless Communications VII and Space Communication Technologies, (2 June 2005); doi: 10.1117/12.604182
Show Author Affiliations
Jing Ma, Univ. of New Orleans (United States)
Xinming Huang, Univ. of New Orleans (United States)
Swapna Kura, Univ. of New Orleans (United States)


Published in SPIE Proceedings Vol. 5819:
Digital Wireless Communications VII and Space Communication Technologies
Rabindra Singh; Raghuveer M. Rao; Sohail A. Dianat; Michael D. Zoltowski, Editor(s)

© SPIE. Terms of Use
Back to Top