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Proceedings Paper

Integrating RET and mask manufacturability in memory designs for local interconnect for sub-100nm trenches
Author(s): Nishrin Kachwala; Walter Iandolo; Travis Brist; Rick Farnbach
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Paper Abstract

Model based OPC for low k1 lithography has a large impact on mask cost, and hence must be optimized with respect to mask manufacturability and mask cost without sacrificing device performance. Design IP blocks not designed with the lithography process in mind (not "litho friendly") require more complex RET/OPC solutions, which can in turn result in unnecessary increases in the mask cost and turn around time. These blocks are typically replicated many times across a design and can therefore have a compounding effect.

Paper Details

Date Published: 5 May 2005
PDF: 9 pages
Proc. SPIE 5756, Design and Process Integration for Microelectronic Manufacturing III, (5 May 2005); doi: 10.1117/12.602539
Show Author Affiliations
Nishrin Kachwala, Cypress Semiconductor Corp. (United States)
Walter Iandolo, Cypress Semiconductor Corp. (United States)
Travis Brist, Mentor Graphics Corp. (United States)
Rick Farnbach, Mentor Graphics Corp. (United States)

Published in SPIE Proceedings Vol. 5756:
Design and Process Integration for Microelectronic Manufacturing III
Lars W. Liebmann, Editor(s)

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