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Proceedings Paper

A new matching engine between design layout and SEM image of semiconductor device
Author(s): Hidetoshi Morokuma; Akiyuki Sugiyama; Yasutaka Toyoda; Wataru Nagatomo; Takumichi Sutani; Ryoichi Matsuoka
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Paper Abstract

Optical proximity correction (OPC) plays a vital role in the lithography process development of current semiconductor devices. OPC is utilized to achieve the ideal pattern shape because of the limitations of optical resolution. However, the lithography process design has become increasingly more complex due to the abundant use of OPC features. Hence, metrology requests for CD-SEM have also become more complex and diverse in order to characterize the critical OPC models. The number of measurement points for OPC model evaluation has increased to several hundred points per layer, and metrology requests for realized pattern shapes on the wafer are no longer simple one-dimensional measurements. Metrology requests include not only the traditional line width measurements, but also edge placement error (EPE) and corner rounding to identify line end shortening. Several researchers have proposed using the design layout as a template instead of the SEM image for the recipe creation of CD-SEM and EPE measurement. However, it is very difficult to achieve good matching results between the design layout and the SEM image in practical processing times. Hitachi High-Technologies has developed a robust and quick matching engine between the design layout and SEM image bitmap. The new system, incorporating this new matching engine, can automatically create a practical recipe from the coordinate information of measurement point and the design layout information, such as GDSII. As a result, the new system can vastly reduce the amount of time and number of operations required to generate a several-hundred point CD-SEM recipe for OPC evaluation. This study demonstrates the capability and presents evaluation results of this new matching engine. This new capability has proven to be a viable solution for OPC evaluation, and its efficiency will allow for quicker information turns between design and manufacturing.

Paper Details

Date Published: 10 May 2005
PDF: 13 pages
Proc. SPIE 5752, Metrology, Inspection, and Process Control for Microlithography XIX, (10 May 2005); doi: 10.1117/12.602066
Show Author Affiliations
Hidetoshi Morokuma, Hitachi High-Technologies Corp. (Japan)
Akiyuki Sugiyama, Hitachi High-Technologies Corp. (Japan)
Yasutaka Toyoda, Hitachi, Ltd. (Japan)
Wataru Nagatomo, Hitachi, Ltd. (Japan)
Takumichi Sutani, Hitachi High-Technologies Corp. (Japan)
Ryoichi Matsuoka, Hitachi High-Technologies Corp. (Japan)


Published in SPIE Proceedings Vol. 5752:
Metrology, Inspection, and Process Control for Microlithography XIX
Richard M. Silver, Editor(s)

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