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Proceedings Paper

Flash memory-cell characterization using two-transistor cell compact macro-model for system-on-chip design
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Paper Abstract

In this paper, we present a systematic methodology to extract two-transistor split-gate flash memory cell model for an accurate DC simulation of SoC designs. Since measured device characteristics require re-design of test-structures with FG contacts, we have used a technology CAD (TCAD) based methodology to develop 2T-cell models for sub-0.18 μm split gate flash memory cells.

Paper Details

Date Published: 17 May 2005
PDF: 8 pages
Proc. SPIE 5755, Data Analysis and Modeling for Process Control II, (17 May 2005); doi: 10.1117/12.601974
Show Author Affiliations
Changyuan Chen, Silicon Storage Technology, Inc. (United States)
Samar Saha, Silicon Storage Technology, Inc. (United States)


Published in SPIE Proceedings Vol. 5755:
Data Analysis and Modeling for Process Control II
Iraj Emami, Editor(s)

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