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Proceedings Paper

Investigating a lithography strategy for diagonal routing architecture at sub-100nm technology nodes
Author(s): Song Li; Ting Chen; Santosh Shah; Ketan Joshi; Kalyan Thumaty; Narain Arora
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Paper Abstract

The X Architecture offers the potential to produce smaller and faster integrated circuits through the pervasive use of 45° wirings on the upper metal layers. The X Initiative members have demonstrated its manufacturability and integration-worthiness at the 130nm, 90nm and 65nm process technology nodes. This paper explores the use of off-axis lithography illumination to print 45° diagonal wires at leading technology nodes. The paper also describes the RET strategies employed for the X Architecture and the effectiveness of various illumination sources at various process nodes. Process window and metal wiring CD variation of Manhattan and X Architecture are compared in the simulations using different types of illuminators. Simulation shows that using 193nm light source, Manhattan and X designs can easily be printed with different types of illuminating source in either 90nm or 65nm process node. Silicon test chips at 90nm that include typical X routing patterns are designed to verify the printability of X Architecture wirings. Electrical measurements as well as SEM analysis are conducted and results show that the fidelity of diagonal wirings is as good as traditional Manhattan routings.

Paper Details

Date Published: 5 May 2005
PDF: 10 pages
Proc. SPIE 5756, Design and Process Integration for Microelectronic Manufacturing III, (5 May 2005); doi: 10.1117/12.601421
Show Author Affiliations
Song Li, Cadence Design Systems, Inc. (United States)
Ting Chen, ASML MaskTools, Inc. (United States)
Santosh Shah, Cadence Design Systems, Inc. (United States)
Ketan Joshi, Cadence Design Systems, Inc. (United States)
Kalyan Thumaty, Cadence Design Systems, Inc. (United States)
Narain Arora, Cadence Design Systems, Inc. (United States)


Published in SPIE Proceedings Vol. 5756:
Design and Process Integration for Microelectronic Manufacturing III
Lars W. Liebmann, Editor(s)

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