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Proceedings Paper

Optical extensions integration for a 0.314-µm2 45-nm node 6-transistor SRAM cell
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Paper Abstract

A target of the 45nm node development at IMEC is to produce a working 6-transistor SRAM (6-T SRAM) cell. Here we describe the lithographic solutions for this challenge. Following the requirements of the ITRS Roadmap requires challenging k1 values. A classical 6-transistor SRAM design is difficult to scale to lower k1 values for imaging and overlay reasons. In this paper we discuss the litho friendly design that was used to originally produce a working 0.314μm2 45nm node 6-transistor SRAM cell. The design was scaled to a k1 value of 0.31 for printing the active area layer on a 0.75NA ArF scanner at IMEC. Later on this was further scaled to a k1 of 0.280 and a cell size of 0.274μm2 for a working cell and imaging with a k1 of 0.265 on a higher NA tool. Various resolution enhancement techniques have been used for the three most critical layers of the SRAM cell: active area, poly gates and contact holes. Although designed unidirectional, the active area and the poly layer of the SRAM cell have critical features in two directions and therefore choosing the right illuminator shape is not straightforward. A pupil shape optimizer was used to maximize the contrast of the aerial image of the various critical features in these layers. For the contact layer the minimal pitch in the design is 160nm, which corresponds to a k1 of 0.31. The pattern was split up into two images to increase the minimum pitch for the imaging to 190nm. Since off-axis illumination is used to print the 190nm pitch, assist features are added to the more sparse features. Contacts are not placed on a regular rectangular grid and additionally non-square contacts are used for local interconnects. This complicates the placement of the assist features and the interference mapping lithography (IML) technology was used to help in this task. The split design has been used in a double patterning approach in the SRAM process flow. In this paper we show that all the above-mentioned resolution enhancement techniques have been successfully integrated and that it resulted in a working 45nm node SRAM cell.

Paper Details

Date Published: 5 May 2005
PDF: 11 pages
Proc. SPIE 5756, Design and Process Integration for Microelectronic Manufacturing III, (5 May 2005); doi: 10.1117/12.600862
Show Author Affiliations
Staf Verhaegen, IMEC vzw (Belgium)
Axel Nackaerts, IMEC vzw (Belgium)
Vincent Wiaux, IMEC vzw (Belgium)
Eric Hendrickx, IMEC vzw (Belgium)
Geert Vandenberghe, IMEC vzw (Belgium)

Published in SPIE Proceedings Vol. 5756:
Design and Process Integration for Microelectronic Manufacturing III
Lars W. Liebmann, Editor(s)

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