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Proceedings Paper

Topography impacts on line-width control for gate level lithography
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Paper Abstract

The dimensional variations caused by topography differences between active and non active shallow trench isolation (STI) areas, at the gate level, need to be controlled through proper use of reflectivity control methods. Line-width variation caused by topography can either be a disastrous problem or so small that it is hard to detect. Some of the primary variables include the step-height, active-area-width and planarization length of the BARC being used. In order to experimentally compare different reflectivity control methods, wafers were built with steps ranging from 7.5 nm higher to 27 nm lower than the surroundings. Organic BARC thicknesses of 90 and 130 nm were evaluated. Two resist thicknesses were also evaluated. Along with examining the effect of step-height, we also examined the effect of active-area-widths ranging from 0.5 um to 4.5 um. The data demonstrate that line-width variation going over this variety of steps is well under 1 nm when BARC and resist thicknesses are optimized.

Paper Details

Date Published: 4 May 2005
PDF: 9 pages
Proc. SPIE 5753, Advances in Resist Technology and Processing XXII, (4 May 2005); doi: 10.1117/12.600697
Show Author Affiliations
Allen H. Gabor, IBM Systems and Technology Group (United States)
Scott D. Halle, IBM Systems and Technology Group (United States)
Chidam Kallingal, Advanced Micro Devices, Inc. (United States)

Published in SPIE Proceedings Vol. 5753:
Advances in Resist Technology and Processing XXII
John L. Sturtevant, Editor(s)

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