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Proceedings Paper

Lithography yield check for IC design
Author(s): Lynn Cai; Ting Chen
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Paper Abstract

As the semiconductor industry goes into the 65nm generation, designs become more complex, mask cost increases exponentially, and the industry is pushing very hard on the lithography process. It is more and more challenging to achieve and maintain acceptable yield. Yield is not only a problem for the Fabs but also an issue that has to be considered by the chip designers. In order to save turn around time, save mask and process development cost and improve the yield, the lithography problems need to be resolved at the design stage. The designers need to be aware of the lithography behavior of their design and be able to modify the design if it causes yield problems in the lithography process. In this paper, we discuss a new tool, a Litho Yield Checker, which can be run stand-alone but is also fully integrated with a Layout Editor, that provides its user with an easy way to visualize how the layouts are to be printed on wafer, and see the common process window (CPW) for the most important locations in the design.

Paper Details

Date Published: 5 May 2005
PDF: 9 pages
Proc. SPIE 5756, Design and Process Integration for Microelectronic Manufacturing III, (5 May 2005); doi: 10.1117/12.600636
Show Author Affiliations
Lynn Cai, Cadence Design Systems, Inc. (United States)
Ting Chen, ASML MaskTools, Inc. (United States)


Published in SPIE Proceedings Vol. 5756:
Design and Process Integration for Microelectronic Manufacturing III
Lars W. Liebmann, Editor(s)

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