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Proceedings Paper

Model-based verification for first time right manufacturing
Author(s): James A. Bruce; Edward W. Conrad; Gregory J. Dick; D. John Nickel; Jacek G. Smolinski
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Paper Abstract

In this paper we will describe the implementation of a system for model-based verification of post OPC data into a manufacturing data flow. Verification is run automatically, upon OPC completion, on the critical levels for every chip run in the 130nm node and beyond to ensure that OPC errors are caught before hardware is committed in the manufacturing line. The checks are derived from the design rule manual, and are written to cover the intent of the design rules. Some of the challenges of implementing a robust model-based verification solution for manufacturing will be discussed, including resource requirements, data management, cycle time, and the creation of a closed loop system to ensure that verification is completed on all chips. The benefits of implementing model-based verification include improved feedback to lithography and OPC teams, enabling constant improvement, as well as increasing the probability of first time right manufacturing of a new chip design.

Paper Details

Date Published: 5 May 2005
PDF: 10 pages
Proc. SPIE 5756, Design and Process Integration for Microelectronic Manufacturing III, (5 May 2005); doi: 10.1117/12.600552
Show Author Affiliations
James A. Bruce, IBM Systems and Technology Div. (United States)
Edward W. Conrad, IBM Systems and Technology Div. (United States)
Gregory J. Dick, IBM Systems and Technology Div. (United States)
D. John Nickel, IBM Systems and Technology Div. (United States)
Jacek G. Smolinski, IBM Systems and Technology Div. (United States)


Published in SPIE Proceedings Vol. 5756:
Design and Process Integration for Microelectronic Manufacturing III
Lars W. Liebmann, Editor(s)

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